EE3203+weekly+review

=EE3203 weekly review=

This page posted all the email sent by course tutor in the 2011/12 sem A.

week 2 ch1 read cycle week 3 week 4


 * Week 2 review**

Calculation the timing of R/W operation is an important topic. If you think reading the lecture notes makes you feel confusing, I suggest you can read the Appendix (and http://www.ee.cityu.edu.hk/~whlau/ee3203/chpt1_appendix.pdf)It teach you how to calculate Tacc and check the conditions step by step. Note that the Tacc you calculated may not satisfy all the conditions. If so, what you need to do is just to increase the no. of cycle to fulfill all the condition.

Some of you asked question about per-charge. It is an essential process to keep the data stored in DRAM. As the voltage level of each cell would drop eventually, it is necessary to keep the voltage in certain level. Assume logic 1 = 3.0V. During per-charge, if Sense Amplifier found that the cell has a voltage level of 1.7V, it will charge it up to 3.0V. Similarly, if the voltage level is 1.3V, it will be pulled low to logic 0.

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**Ch 1 Read Cycle**

How to read the read cycle in Cantonese. || 呢幅係已經COMBINE左GE timing diagram，無論咩U同SRAM都係出呢幾行
 * from p.17 of ch1 lecture note

咁ADDR 由放個ADD落去到ADDRESS VALID就有個DELAY叫TRAD ADDRESS VALID到DATA VALID(就係中間條虛線)就係tAA address valid之後要搵個address係邊再比chip enable,中間個DELAY就係TDEC(decoder delay),通常都唔係RAM/CPU ge datasheet度搵， depends on decoder,如果有decoder ge datasheetT就搵到，唔係就要計
 * ADDR**

nCE要睇ge都係佢喺decoder delay之後開始
 * nCE**

nOE ge開始位唔重要可能早/遲過nCE,佢開始前個delayDELAY係由第一條虛線開始睇，即係啱啱放左ADDRESS落去，未address valid ge時候 咁nOE要留意OE access time tDOE,佢係由nOE=0開始到data valid
 * nOE**

data度一開始有斜線代表data unstable,我地要確保用GE data係stable ge,所以之前幾樣都考慮緊去到data valid ge 時間 data setup time(tRDS) 係指成功read到data需要ge時間，多左冇所謂,多左ge就叫margin,好多時計數都SET做0
 * DATA**

READ完之後CPU會放另一個address出黎，DATA會留係DATA BUS多陣先REMOVE，嗰段時間就係data hold time tRDH
 * After data setup**

去返3條式，第一條係睇ADDRESS GE,會見到係講緊個READ CYCLE要長過address delay+addres access(taa)+data hold time(trds)
 * Calculation**

第二條同address decode到要俾chip select 有關，個READ CYCLE要長過chip select delay(trcd)+decoder delay+ce access time(tacs)+data hold time

第三條就係同output有關，個READ CYCLE要長過OE delay+oe access time+data hold time ||

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**Week 3 review**

For the read cycle:

1. Draw the margin area

2. Draw a THICK line between "data unstable" and "data valid"

3. Focus on the THICK line, mark the corresponding symbols on ADDR, nCE and nOE according to another read cycle timing diagram.

P.S. You should also mark the tDEC(decorder delay) on nGCSx. tDEC is from the position of nGCS drops to the position of nCE drops

For the write cycle,

1. Draw the tWC on EXTCLK. Its position is right shift whole Tacc range for half period.

2. Draw a THICK line at Write End. (Write End position: nWE rise from 0 to 1)

3. Focus on the THICK line, mark the corresponding symbols on ADDR, nCE, nWE and DATA according to another write cycle timing diagram.

P.S. You should also mark the tDEC(decorder delay) on nGCSx. tDEC is from the position of nGCS drops to the position of nCE drops

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**Week 4 review**

After last few week of drawing timing diagram of SRAM, the later part of chapter 1 is mainly about DRAM and Synchronous DRAM(SDRAM).

<span style="font-family: 'PrimaSans BT,Verdana,sans-serif';">One thing you should bear in mind is even the no of bits of addresses are the same, <span style="font-family: 'PrimaSans BT,Verdana,sans-serif';">the physical address pins of DRAM/SDRAM will be less than SRAM. <span style="font-family: 'PrimaSans BT,Verdana,sans-serif';">Since address of DRAM is divided into two parts: row and column and <span style="font-family: 'PrimaSans BT,Verdana,sans-serif';">the address is sent in the order RAS->row address->CAS->column address, <span style="font-family: 'PrimaSans BT,Verdana,sans-serif';">the number of address bits sent at a time is less than the whole address. <span style="font-family: 'PrimaSans BT,Verdana,sans-serif';">You can refer to p.24 for this.

<span style="font-family: 'PrimaSans BT,Verdana,sans-serif';">Many of you asked about precharge and refresh. <span style="font-family: 'PrimaSans BT,Verdana,sans-serif';">Precharge is a process used to reduce time used in write(or DRAM reading the data stored in the memory cell p.27), <span style="font-family: 'PrimaSans BT,Verdana,sans-serif';">but refresh is required periodically for DRAM. <span style="font-family: 'PrimaSans BT,Verdana,sans-serif';">As DRAMs' cell capacitor may have leakage, a periodical refresh is required to avoid data loss. <span style="font-family: 'PrimaSans BT,Verdana,sans-serif';">It has the highest piority. This is a very importance characteristic of DRAM.

<span style="font-family: 'PrimaSans BT,Verdana,sans-serif';">For pre-charge, it is used when writing data to DRAM. <span style="font-family: 'PrimaSans BT,Verdana,sans-serif';">First, DRAM is precharged to Vcc/2 before writing. <span style="font-family: 'PrimaSans BT,Verdana,sans-serif';">Then, there will be maximum Vcc/2 charge of difference no matter the result is logic 1 or 0. <span style="font-family: 'PrimaSans BT,Verdana,sans-serif';">Imagine a bit with original logic 1 and the new data is logic 0, <span style="font-family: 'PrimaSans BT,Verdana,sans-serif';">the maximum change will be Vcc. <span style="font-family: 'PrimaSans BT,Verdana,sans-serif';">With precharge, the time for writing will be reduced.

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